MCF51QH128 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MCF51QH128' PDF : 68 Pages View PDF
SS1
(OUTPUT)
Communication interfaces
3
2
10
SPSCK
(CPOL = 0)
5
(OUTPUT)
5
11
4
SPSCK
(CPOL = 1)
(OUTPUT)
10
11
6
7
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
MOSI
(OUTPUT)
MSB OUT2
8
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=0)
SS1
(OUTPUT)
SPSCK
(CPOL = 0)
(OUTPUT)
SPSCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
2
3
5
5
6
7
MSB IN2
8
(OUMTPOUSTI)PORT DATA MASTER MSB OUT2
10
10
BIT 6 . . . 1
9
BIT 6 . . . 1
11
4
11
LSB IN
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI master mode timing (CPHA=1)
Num.
1
Table 33. SPI slave mode timing
Symbol Description
fop
Frequency of operation
Min.
0
Max.
fBUS/4
Table continues on the next page...
PORT DATA
Unit
Hz
Comment
fBUS is the
bus clock
as defined
in Table 8.
MCF51QH128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
47
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