MCF51QH128 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MCF51QH128' PDF : 68 Pages View PDF
Communication interfaces
Table 33. SPI slave mode timing (continued)
Num.
2
Symbol Description
tSPSCK SPSCK period
Min.
4 x tBUS
Max.
—
3
tLead Enable lead time
4
tLag
Enable lag time
5
tWSPSCK Clock (SPSCK) high or low time
6
tSU
Data setup time (inputs)
7
tHI
Data hold time (inputs)
8
ta
Slave access time
1
—
1
—
tBUS - 30
—
19.5
—
0
—
—
tBUS
9
tdis
Slave MISO disable time
10
tv
Data valid (after SPSCK edge)
11
tHO
Data hold time (outputs)
12
tRI
Rise time input
tFI
Fall time input
13
tRO
Rise time output
tFO
Fall time output
—
tBUS
—
27
0
—
—
tBUS - 25
—
25
Unit
ns
tBUS
tBUS
ns
ns
ns
ns
ns
ns
ns
ns
Comment
tBUS = 1/
fBUS
—
—
—
—
—
Time to
data active
from high-
impedanc
e state
Hold time
to high-
impedanc
e state
—
—
—
ns
—
SS
(INPUT)
SPSCK
(CPOL = 0)
(INPUT)
SPSCK
(CPOL = 1)
(INPUT)
8
MISO
(OUTPUT)
2
12
3
5
5
12
10
nsoetee
SLAVE MSB BIT 6 . . . 1
13 4
13
9
11
11
SLAVE LSB OUT
SEE
NOTE
MOSI
(INPUT)
6
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined!
Figure 20. SPI slave mode timing (CPHA=0)
MCF51QH128 Advance Information Data Sheet, Rev. 0, 05/2011.
48
Preliminary
Freescale Semiconductor, Inc.
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