MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
Table 3-1. Pin Description (5 of 6)
Pin Name
Pin No.
I/O
SDADDR[12:0]
SDCASn
V20,W20,Y20,
O
W19,Y19,W18,
Y18,W17,Y17,V
16,W16,Y16,V1
5
U20
O
SDRASn
V19
O
SDWRn
V18
O
SDCSn
V17
O
SDCLK100MHz
M19
O
USB_Dp
B8
I/O
USB_Dn
C8
I/O
SDAA_PWRCLK
E1
I/O
SDAA_PWRCLKn
E2
I/O
SDAA_DIBp
E4
I/O
SDAA_DIBn
E3
I/O
EV_VD[0]/EADC_D[4]/ MREQn W12
I/O
EV_VD[1]/EADC_D[5]
U12
I/O
EV_VD[2]/EADC_D[6]/ OPCn Y13
I/O
EV_VD[3]/EADC_D[7]
W13
I/O
EV_VD[4]/EADC_D[8]/ MAS[0] U13
I/O
EV_VD[5]/EADC_D[9]/ MAS[1] Y14
I/O
EV_VD[6]/EADC_D[10]
W14
I/O
EV_VD[7]/EADC_D11]/
V14
I/O
ABORT
EV_CLK
W_Rn
V13
I
N19
O
XAKn
N18
O
Input
Type
-
-
-
-
-
5VT
3V
3V
3V
3V
3V
3V
3V
3V
H3V
D5VT
U5VT
Output
Type
2XT3V
Pin Description
Countach (S)DRAM address bus (13 pins)
2XT3V
2XT3V
2XT3V
2XT3V
2XT5VT
2XT3V
2XT3V
2XT3V
2XT3V
2XT3V
2XT3V
2XT3V
2XT3V
-
2XT5VT
2XT5VT
Countach (S)DRAM column address strobe (active
low)
Countach (S)DRAM row address strobe (active
low)
Countach (S)DRAM write strobe (active low)
Countach (S)DRAM chip select
Countach (S)DRAM clock
Positive data input/output pin for USB
Negative data input/output pin for USB
Positive power/clock output from SSD
Negative power/clock output from SSD
Positive data input/output pin for SDAA
Negative data input/output pin for SDAA
External video data [0] input for VIP or external
ADC data [4] input or Memory Request (active
low)-indicates that the following cycle is a memory
access.
External video data [1] input for VIP or external
ADC data [5] input
External video data [2] input for VIP or external
ADC data [6] input or Op Code fetch (active low)-
LOW indicates that the processor is fetching an
instruction from memory.
External video data [3] input for VIP or external
ADC data [7] input
External video data [4] input for VIP or external
ADC data [8] input or Memory access size
MAS[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 -
Reserved during the normal operation
External video data [5] input for VIP or external
ADC data [9] input or Memory access size
MAS[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 -
Reserved during the normal operation
External video data [6] input for VIP or external
ADC data [10] input
External video data [7] input for VIP or external
ADC data [11] input or aborted bus cycle-the
address selected is outside of CS’s address
ranges.
(Hysteresis) External video clock input
(Pull down) The bus access is a read operation
when W_Rn is LOW and write when W_Rn is
HIGH.
(Pull up) SIU Transaction Acknowledge. The
D[15:0] data will be transferred during this MCLK
cycle.
100723A
Conexant
3-5
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