MFC2000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'MFC2000' PDF : 426 Pages View PDF
MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
Pin Name
DMACYC/ CLK_CONFIG[2]
WAITn
CACHEHIT/
JTAG_MODE_SEL
SEQ
SSD_DIBRX
TX_DATA
SDAA_GPIO_INT
VSS
VDD
P80VSS
P80VDD
VGG1
VGG2
VGG3
VGG4
VDRAM
VRTC
(NC)
Table 3-1. Pin Description (6 of 6)
Pin No.
I/O
M18
I/O
J17
O
J18
I/O
N17
O
F3
O
F2
O
F1
O
L1,L2,L3,L4,U1
-
0,V10,W10,Y10,
L17,L18,L19,L2
0,A11,B11,C11,
D11
A10,B10,C10,K
-
1,K2,K3,K4,U11
,V11,W11,Y11,
K17,M20
M1
-
M2
-
M17
-
D14
-
D5
-
M4
-
E18
-
F17
-
A3,B3,A4,B4,C4 -
,D4,A5,B5,C5,A
6,B6,C6,D6,A7,
B7,C7,D7,D8
Input
Type
U5VT
U5VT
U5VT
D5VT
Output
Type
2XT5VT
2XT5VT
2XT5VT
2XT5VT
Pin Description
(Pull up) DMA Cycle-the DMA logic has control of
the external bus. (CLK_CONFIG[2] input during the
reset period)
(Pull up) Wait (active low)-reflects the wait states
being used by the ARM processor.
(Pull up) Cache hit-the ARM is retrieving data from
the cache memory (JTAG_MODE_SEL during the
reset period, “1” – ARM JTAG selected
(Pull down) Sequential Address Access. (Used
with nMREQ to indicate memory access type. Only
required if using co-processor cycles)
Internal test pin. Leave it open.
Internal test pin. Leave it open.
Internal test pin. Leave it open.
Digital ground (16 pins)
+3.3V digital power (13 pins)
Digital ground for P80 DSP
+3.3V digital power for P80 DSP
+5V Power for the +5V tolerant pads
+5V Power for the +5V tolerant pads
+5V Power for the +5V tolerant pads
+5V Power for the +5V tolerant pads
Battery Power for DRAM refresh.
Battery Power for RTC
18 RESERVED pins
3-6
Conexant
100723A
Share Link: 
