
ML2722
SYMBOL
PARAMETER
TIME (ns)
tR
Clock input rise time
15
tF
Clock input fall time
15
tCK
Clock period
>50
tW
Minimum pulse width
2000
tD
Delay from last clock falling edge
>15
tSE
Enable setup time to ignore next rising clock
>15
tS
Data-to-clock setup time
>15
tH
Data-to-clock hold time
>15
Table 3. 3-Wire Bus Timing Characteristics
CLK
DATA
EN
tF
tS
tH
tR
tSE
tCK
tD
MSB
DB13
DB12
DB11
REGISTER DATA (14 BITS)
DB0
ADR1
LSB
ADR0
tW
ADDRESS DATA (2 BITS)
Figure 4. Serial Bus Timing for Address and Data Programming
DS2722-F-06
FINAL DATASHEET
DECEMBER 2005 19