ML2722DH-T View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2722DH-T' PDF : 28 Pages View PDF
ML2722
REGISTER #0, PLL CONFIGURATION
PLL Charge Pump Polarity (QPP): DB0
This bit sets the charge pump polarity to sink or source current. For a majority of applications, this bit is cleared (QPP =
0). For applications where an external amplifier is in the loop filter, this bit is set to 1 to change the charge pump polarity
(see Table 7).
QPP
0
1
PLL CHARGE PUMP POLARITY
Frequency signal < frequency reference. Charge pump sources current.
Frequency signal < frequency reference. Charge pump sinks current.
Table 7. PLL Charge Pump Polarity
Reference Divide Bit Zero (RD0): DB1
This bit sets the reference division of the PLL to either 6 or 12 (see Table 8).
RD0 REFERENCE DIVISION NOMINAL REFERENCE FREQUENCY
0
6
1
12
6.144MHz
12.288MHz
Table 8. Reference Frequency Select
Receive Closed Loop Bit (RXCL): DB2
This bit is used in Receive mode to put the PLL into either open loop or closed loop (see Table 9).
RXCL RECEIVE PLL MODE
0
PLL open loop
1
PLL closed loop
Table 9. PLL Mode in Normal Receive Operation
PLL Frequency Shift Bit (LOL): DB3
LO shift for transmit and receive. For normal operations, it is recommended that LOL = 0 (see Table 10).
LOL LO SHIFT FOR TRANSMIT LO SHIFT FOR RECEIVE
0
0
1
+1.024MHz
+1.024MHz
0
Table 10. PLL Frequency Shift
DS2722-F-06
FINAL DATASHEET
DECEMBER 2005 23
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