ML2722DH-T View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2722DH-T' PDF : 28 Pages View PDF
ML2722
REGISTER #2, FILTER TUNING SELECT TEST MODE
Analog Test Control Bits (ATM): <DB2:DB0>
The test mode selected is described in Table 14. The performance of the ML2722 is not specified in these test modes.
Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default
(power-up) state of these bits is ATM<2:0> = <0,0,0>. When a non-zero value is written to the field, RSSI/TPI (pin 28)
and TPC/TPQ (pin 7) become analog test access ports, giving access to the outputs of key signal processing stages in
the transceiver. During normal operation, the ATM field should be set to zero.
ATM2 ATM1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
ATM0
RSSI/TPI
TPC/TPQ
0
RSSI
TPC (PA Control)
1
I No Connect
Q No Connect
0
I IF Buffer Output
Q IF Buffer Output
1
I IF Buffer Output
Q IF Buffer Output
0
I IF Buffer Output
Q IF Buffer Output
1
I Data Slicer Input
Q Data Slicer Input
0
I IF Limiter Outputs
Q IF Limiter Outputs
1
1.67V Ref.
VCO Mod. Voltage
Table 14. Analog Test Control Bits
Digital Test Control Bits (DTM): <DB2:DB0>
The DTM<2:0> bit functions are described in Table 15. The performance of the ML2722 is not specified in these test
modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The
default (power-up) state of these bits is DTM<2:0> = <0,0,0>. When a non-zero value is written to these fields, DOUT
(pin 32) becomes a digital test access port for key digital signals in the transceiver. During normal operation, the DTM
field should be set to zero.
DTM2 DTM1 DTM0
DOUT
0
0
0
0
0
1
0
1
0
Demodulated data
1
Receiver AGC state
0
PLL Main Divider Output
1
PLL Reference Divider Output
Table 15. Digital Test Control Bits
TRANSMIT AND RECEIVE DATA INTERFACES
The DIN and DOUT CMOS logic levels are serial data that correspond to FSK modulated data on the radio channel.
The ML2722 operates as an FSK transceiver in the 902 to 928MHz ISM band. The chip rate, bit rate and spreading
code are controlled by the baseband processor, and the FM deviation and transmit filtering are controlled by the
transceiver.
DIN provides data to the Transmit data filter, which band limits the transmitted chips or bits before they are FM
modulated. There is no re-timing of the chips or bits, so the transmitted FSK chips or bits take their timing from DIN (pin
30). In the Receive chain, FM demodulation, data filtering, and data slicing take place in the ML2722 receiver, with chip,
bit and word rate timing recovery performed in the baseband processor.
RSSI AND REF
There are two other interface pins between the ML2722 transceiver and the baseband IC: the RSSI/TPI (pin 28) and
REF (pin 9).
DS2722-F-06
FINAL DATASHEET
DECEMBER 2005 25
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