ML9042-XX View Datasheet(PDF) - LAPIS Semiconductor Co., Ltd.
Part Name
Description
MFG CO.
'ML9042-XX' PDF : 58 Pages View PDF
LAPIS Semiconductor
FEDL9042-01
ML9042-xx
Built-in Reset Circuit
The ML9042 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is “1” and the ML9042 does not accept any instruction from the CPU
(other than the Read BF instruction).
The Busy Flag is “1” for about 15 ms after the VDD becomes 2.7 V or higher.
During this initialization, the ML9042 performs the following instructions:
1) Display clearing
2) CPU interface data length = 8 bits
3) 1-line LCD display
4) ADC counting = Increment
5) Display shifting = None
6) Display = Off
7) Cursor = Off
8) Blinking = Off
9) Arbitrator = Displayed in the lower line
10) Arbitrator = Not displayed
11) Segment shift direction = SEG1 SEG100
12) Common shift direction = COM1 COM17
(DL = “1”)
(N = “0”)
(I/D = “1”)
(S = “0”)
(D = “0”)
(C = “0”)
(B = “0”)
(AS = “0”)
(ABE = “0”)
(SSR = “0”)
(CSR = “0”)
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the
built-in reset circuit may not work properly. In such a case, initialize the ML9042 with the instructions from the
CPU. The use of a battery always requires such initialization from the CPU. (See “Initial Setting of Instructions”)
2.7 V
0.2 V
tON
0.1 ms tON 100 ms
0.2 V
tOFF
1 ms tOFF
Figure 1 Power-on and Power-off Waveform
0.2 V
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