ML9042-XX View Datasheet(PDF) - LAPIS Semiconductor Co., Ltd.
Part Name
Description
MFG CO.
'ML9042-XX' PDF : 58 Pages View PDF
LAPIS Semiconductor
FEDL9042-01
ML9042-xx
Serial Interface Mode
In the Serial I/F Mode, the ML9042 interfaces with the CPU via the RS0/CSB, E/SHTB, RW/SI, and DB0(SO)
pins.
Writing and reading operations are executed in units of 16 bits after the RS0/CSB signal falls down. If the RS0/CSB
signal rises up before the completion of 16-bit unit access, this access is ignored.
When the BF bit is “1”, the ML9042 cannot accept any other instructions. Before inputting a new instruction,
check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.
Data format is LSB-first.
Examples of Access in the Serial I/F Mode
1) WRITE MODE
RS0/CSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
E/SHTB
BUSY
(Internal operation)
RWB/SI
1
1
1
1
1 R/W RS0 RS1 D0 D1 D2 D3 D4 D5 D6 D7
1
DB(SO)
2) READ MODE
RS0/CSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
E/SHTB
BUSY
(Internal operation)
RWB/SI
1 1 1 1 1 R/W RS0 RS1
1
DB(SO)
D0 D1 D2 D3 D4 D5 D6 D7
Note 1: Higher 5 bits of each instruction must be input at a “H” level.
Note 2: Lower 8 bits are “don’t care” when the instructions in the READ MODE are set.
Note 3: After one instruction is input, the next instruction must be input after the RS0/CSB pin is pulled at a “H”
level.
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