MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 78 Pages View PDF
1
SCK
( CLKPOL = 0 )
Input
SCK
( CLKPOL = 1 )
Input
SS
Input
2
2
3
8
9
4
5
MOSI
Input
6
7
MISO
Output
Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Sym
Description
Min
1
SCK cycle time, programable in the PSC CCS register
30.0
2
SCK pulse width, 50% SCK duty cycle
15.0
3
Slave select clock delay, programable in the PSC CCS register 30.0
4
Output data valid
—
5
Input Data setup time
6.0
6
Input Data hold time
1.0
7
Slave disable lag time
—
8 Sequential Transfer delay, programable in the PSC CTUR / CTLR 15.0
register
9
Clock falling time
—
10
Clock rising time
—
Max Units SpecID
—
ns A15.46
—
ns A15.47
—
ns A15.48
8.9
ns A15.49
—
ns A15.50
—
ns A15.51
8.9
ns A15.52
—
ns A15.53
7.9
ns A15.54
7.9
ns A15.55
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
52
Freescale Semiconductor
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