1.3.18 IEEE 1149.1 (JTAG) AC Specifications
Table 51. JTAG Timing Specification
Sym
Characteristic
Min
Max
—
TCK frequency of operation.
0
25
1
TCK cycle time.
40
—
2
TCK clock pulse width measured at 1.5V.
1.08
—
3
TCK rise and fall times.
0
3
4
TRST setup time to tck falling edge(1).
10
—
5
TRST assert time.
5
—
6
Input data setup time(2).
5
—
7
Input data hold time(2).
15
—
8
TCK to output data valid(3).
0
30
9
TCK to output high impedance(3).
0
30
10
TMS, TDI data setup time.
5
—
11
TMS, TDI data hold time.
1
—
12
TCK to TDO data valid.
0
15
13
TCK to TDO high impedance.
0
15
1 TRST is an asynchronous signal. The setup time is for test purposes only.
2 Non-test, other than TDI and TMS, signal input timing with respect to TCK.
3 Non-test, other than TDO, signal output timing with respect to TCK.
1
2
2
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SpecID
A17.1
A17.2
A17.3
A17.4
A17.5
A17.6
A17.7
A17.8
A17.9
A17.10
A17.11
A17.12
A17.13
A17.14
TCK
VM
VM
VM
3
3
VM = Midpoint Voltage
Numbers shown reference Table 51.
Figure 46. Timing Diagram—JTAG Clock Input
TCK
TRST
56
4
5
Numbers shown reference Table 51.
Figure 47. Timing Diagram—JTAG TRST
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor