MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 78 Pages View PDF
SCK
( CLKPOL = 0 )
Output
SCK
( CLKPOL = 1 )
Output
SS
Output
1
10
9
2
2
9
10
3
7
8
MOSI
Output
MISO
Input
4
5
6
Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)
Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym
Description
Min
1
SCK cycle time, programable in the PSC CCS register
30.0
2
SCK pulse width, 50% SCK duty cycle
15.0
3
Slave select clock delay
0.0
4
Output data valid
—
5
Input Data setup time
2.0
6
Input Data hold time
1.0
7
Slave disable lag time
0.0
8 Minimum Sequential Transfer delay = 2 × IP-Bus clock cycle time 30.0
Max Units SpecID
—
ns A15.56
—
ns A15.57
—
ns A15.58
14.0
ns A15.59
—
ns A15.60
—
ns A15.61
—
ns A15.62
—
ns A15.63
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
53
Share Link: 
