Sym
1
2
Table 30. Timing Specification ata_isolation
Description
ata_isolation setup time
ata_isolation hold time
Min
Max
7
—
—
19
Units
IP Bus cycles
IP Bus cycles
SpecID
A8.48
A8.49
DIOR
ATA_ISOLATION
1
2
Figure 26. Timing Diagram—ATA-ISOLATION
1.3.10 Ethernet
AC Test Timing Conditions:
• Output Loading
All Outputs: 25 pF
Table 31. MII Rx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t1
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
10
—
ns
A9.1
t2
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
10
—
ns
A9.2
t3
RX_CLK pulse width high
35%
65%
RX_CLK Period(1)
A9.3
t4
RX_CLK pulse width low
35%
65%
RX_CLK Period(1)
A9.4
1 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.
t3
RX_CLK (Input)
t4
RXD[3:0] (inputs)
RX_DV
RX_ER
t1
t2
Figure 27. Ethernet Timing Diagram—MII Rx Signal
MPC5200B Data Sheet, Rev. 4
38
Freescale Semiconductor