MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 72 Pages View PDF
Table 34. MII Serial Management Channel Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t10
MDC falling edge to MDIO output delay
0
25
ns
A9.10
t11
MDIO (input) to MDC rising edge setup
10
—
ns
A9.11
t12
MDIO (input) to MDC rising edge hold
10
—
ns
A9.12
t13
MDC pulse width high(1)
160
—
ns
A9.13
t14
MDC pulse width low(1)
160
—
ns
A9.14
t15
MDC period(2)
400
—
ns
A9.15
1 MDC is generated by MPC5200B with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control
register is changed during operation. See the MPC5200B User’s Manual (MPC5200BUM).
2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5200B User’s Manual
(MPC5200BUM).
t13
MDC (Output)
t14
t15
t10
MDIO (Output)
MDIO (Input)
t11 t12
Figure 30. Ethernet Timing Diagram—MII Serial Management
1.3.11 USB
Table 35. Timing Specifications—USB Output Line
Sym
Description
Min
Max
1
USB Bit width(1)
83.3
667
2
Transceiver enable time
83.3
667
3
Signal falling time
—
7.9
4
Signal rising time
—
7.9
1 Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode).
NOTE
Output timing is specified at a nominal 50 pF load.
Units
ns
ns
ns
ns
SpecID
A10.1
A10.2
A10.3
A10.4
MPC5200B Data Sheet, Rev. 4
40
Freescale Semiconductor
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