MPC5200B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5200B' PDF : 72 Pages View PDF
Table 32. MII Tx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t5
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER
5
—
invalid
ns
A9.5
t6 TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid —
25
ns
A9.6
t7
TX_CLK pulse width high
35%
65%
TX_CLK Period(1)
A9.7
t8
TX_CLK pulse width low
35%
65%
TX_CLK Period(1)
A9.8
1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 Specification.
t7
TX_CLK (Input)
t5
t8
TXD[3:0] (Outputs)
TX_EN
TX_ER
t6
Sym
t9
Figure 28. Ethernet Timing Diagram—MII Tx Signal
Table 33. MII Async Signal Timing
Description
CRS, COL minimum pulse width
Min
Max
1.5
—
Unit
SpecID
TX_CLK Period A9.9
CRS, COL
t9
Figure 29. Ethernet Timing Diagram—MII Async
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
39
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