MPC5567 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5567' PDF : 56 Pages View PDF
Electrical Characteristics
3.13.9 eQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics (pads at 3.3V or at 5.0V) 1
CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
Num
Rating
Symbol
Min
Typ
Max
Unit
1 FCK Frequency 2, 3
fFCK
1/17
—
1/2
fSYS_CLK
2 FCK Period (tFCK = 1/ fFCK)
tFCK
2
—
17
tSYS_CLK
3 Clock (FCK) High Time
tFCKHT
tSYS_CLK − 6.5
—
9* tSYS_CLK + 6.5
ns
4 Clock (FCK) Low Time
tFCKLT
tSYS_CLK − 6.5
—
8* tSYS_CLK + 6.5
ns
5 SDS Lead/Lag Time
tSDS_LL
–7.5
—
+7.5
ns
6 SDO Lead/Lag Time
tSDO_LL
–7.5
—
+7.5
ns
7 EQADC Data Setup Time (Inputs)
tEQ_SU
22
—
—
ns
8 EQADC Data Hold Time (Inputs)
tEQ_HO
1
—
—
ns
1 SS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 50pF with SRC = 0b11.
2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
FCK
SDS
SDO
External Device Data Sample at
FCK Falling Edge
SDI
EQADC Data Sample at
FCK Rising Edge
2
3
4
5
4
6
1st (MSB)
25th
5
2nd
26th
8
7
1st (MSB) 2nd
25th
26th
Figure 27. EQADC SSI Timing
MPC5567 Microcontroller Data Sheet, Rev. 0
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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