MPC5567 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5567' PDF : 56 Pages View PDF
Electrical Characteristics
3.14.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising
or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of
non-compliant MII PHYs.
Refer to the ethernet chapter of the device Reference Manual for details of this option and how to enable it.
Table 29 lists MII transmit channel timings.
Table 29. MII Transmit Signal Timing
Num
5
6
7
8
Characteristic
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
TX_CLK pulse width high
TX_CLK pulse width low
Min
5
—
35%
35%
Max
—
25
65%
65%
Unit
ns
ns
TX_CLK period
TX_CLK period
Figure 29 shows MII transmit signal timings listed in Table 29.
M7
TX_CLK (input)
TXD[3:0] (outputs)
TX_EN
TX_ER
M5
M8
M6
Figure 29. MII Transmit Signal Timing Diagram
MPC5567 Microcontroller Data Sheet, Rev. 0
46
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Share Link: 
