VIN
VDD
VIH
VIL
VHYS
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
Figure 5. I/O input DC electrical characteristics definition
Table 13. I/O input DC electrical characteristics
Symbol C
Parameter
Conditions1
Value2
Unit
Min
Typ
Max
VIH SR P Input high level CMOS (Schmitt
Trigger)
—
0.65VDD — VDD + 0.4 V
VIL SR P Input low level CMOS (Schmitt
Trigger)
—
0.3
— 0.35VDD
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
—
0.1VDD
—
—
ILKG CC P Digital input leakage
P
D
No injection TA = 40 °C —
2
— nA
on adjacent
pin
TA = 25 °C
—
2
—
TA = 105 °C —
12
500
P
WFI SR P Width of input pulse rejected by
analog filter3
TA = 125 °C —
—
—
70
1000
—
404 ns
WNFI SR P Width of input pulse accepted by
—
10004
—
—
ns
analog filter(3)
1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2 VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3 Analog filters are available on all wakeup lines.
4 The width of input pulse in between 40 ns to 1000 ns is indeterminate. It may pass the noise or may not depending
on silicon sample to sample variation.
4.6.3 I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
MPC5646C Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
47