3 VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the
end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC0_S depend on programming.
5 Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
6 Refer to ADC conversion table for detailed calculations.
7 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
4095
4094
4093
4092
4091
4090
Offset Error OSE
Gain Error GE
1 LSB ideal = AVDD / 4096
(2)
code out
7
6
5
(5)
4
(4)
3
2
(3)
1
1 LSB (ideal)
0
1 23 45 67
Offset Error OSE
(1)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Figure 20. ADC_1 characteristic and error definitions
MPC5646C Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
79