MPC8349VVAGDB View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVAGDB

PowerQUICC II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

Prev 51 52 53 54 55 56 57 58 59 60 Next

Figure 37 provides the AC test load for the SPI.

Output

Z0 = 50 Ω

Package and Pin Listings

RL = 50 Ω

OVDD/2

Figure 37. SPI AC Test Load

Figure 38 and Figure 39 represent the AC timings from Table 54. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 38 shows the SPI timings in slave mode (external clock).

SPICLK (Input)

Input Signals:

SPIMOSI

(See Note)

tNEIVKH

tNEIXKH

Output Signals:

SPIMISO

(See Note)

tNEKHOX

Note: The clock edge is selectable on SPI.

Figure 38. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 39 shows the SPI timings in master mode (internal clock).

SPICLK (Output)

Input Signals:

SPIMISO

(See Note)

tNIIVKH

tNIIXKH

Output Signals:

SPIMOSI

(See Note)

tNIKHOX

Note: The clock edge is selectable on SPI.

Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram

18 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8349EA is available

in a tape ball grid array (TBGA). See Section 18.1, “Package Parameters for the MPC8349EA TBGA” and

Section 18.2, “Mechanical Dimensions for the MPC8349EA TBGA.

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

53

Share Link: