MPC8349VVAGFB View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8349VVAGFB
Freescale Semiconductor
'MPC8349VVAGFB' PDF : 87 Pages View PDF
Clocking
19 Clocking
Figure 41 shows the internal distribution of the clocks.
e300 Core
Core PLL
core_clk
CFG_CLKIN_DIV
CLKIN
csb_clk
To DDR
Memory
Controller DDR
6
Clock
ddr_clk
Div
6
System PLL
Clock
Unit lbiu_clk
/2
/n
To Local Bus
Memory LBIU
Controller DLL
csb_clk to Rest
of the Device
MCK[0:5]
MCK[0:5]
DDR
Memory
Device
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
Local Bus
Memory
Device
PCI_CLK/
PCI_SYNC_IN
PCI Clock
Divider
PCI_SYNC_OUT
8
PCI_CLK_OUT[0:7]
Figure 41. MPC8349EA Clock Subsystem
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8349EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8349EA to function. When the
device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal
should be tied to GND.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
66
Freescale Semiconductor
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