MPC8349VVAGFB View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8349VVAGFB
Freescale Semiconductor
'MPC8349VVAGFB' PDF : 87 Pages View PDF
Clocking
Table 60. CSB Frequency Options for Agent Mode (continued)
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk :
Input Clock Ratio2
Input Clock Frequency (MHz)2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0110
6:1
100
150
200
Low
0111
7:1
116
175
233
Low
1000
8:1
133
200
266
Low
1001
9:1
150
225
300
Low
1010
10 : 1
166
250
333
Low
1011
11 : 1
183
275
Low
1100
12 : 1
200
300
Low
1101
13 : 1
216
325
Low
1110
14 : 1
233
Low
1111
15 : 1
250
Low
0000
16 : 1
266
High
0010
4:1
100
133
266
High
0011
6:1
100
150
200
High
0100
8:1
133
200
266
High
0101
10 : 1
166
250
333
High
0110
12 : 1
200
300
High
0111
14 : 1
233
High
1000
16 : 1
266
1 CFG_CLKIN_DIV doubles csb_clk if set high.
2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
19.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 61 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 61 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
71
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