Clocking
19.3 Suggested PLL Configurations
Table 62 shows suggested PLL configurations for 33 and 66 MHz input clocks.
Table 62. Suggested PLL Configurations
RCWL
400 MHz Device
533 MHz Device
Ref
No.1 SPMF
CORE
PLL
Input
Clock
Freq
(MHz)2
922 1001 0100010 —
723 0111 0100011 33
604 0110 0000100 33
624 0110 0100100 33
803 1000 0000011 33
823 1000 0100011 33
903 1001 0000011
923 1001 0100011
704 0111 0000011
724 0111 0100011
A03 1010 0000011
804 1000 0000100
705 0111 0000101
606 0110 0000110
904 1001 0000100
805 1000 0000101
A04 1010 0000100
304 0011 0000100 66
324 0011 0100100 66
403 0100 0000011 66
423 0100 0100011 66
305 0011 0000101
503 0101 0000011
404 0100 0000100
CSB
Freq
(MHz)
Core
Freq
(MHz)
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
33 MHz CLKIN/PCI_CLK Options
—
—
—
—
233
350
33
233
200
400
33
200
200
400
33
200
266
400
33
266
266
400
33
266
—
33
300
—
33
300
—
33
233
—
33
233
—
33
333
—
33
266
—
—
—
—
—
—
—
—
—
—
66 MHz CLKIN/PCI_CLK Options
200
400
66
200
200
400
66
200
266
400
66
266
266
400
66
266
—
66
200
—
66
333
—
66
266
Core
Freq
(MHz)
f300
350
400
400
400
400
450
450
466
466
500
533
400
400
400
400
500
500
533
667 MHz Device
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
Core
Freq
(MHz)
33
300
300
33
233
350
33
200
400
33
200
400
33
266
400
33
266
400
33
300
450
33
300
450
33
233
466
33
233
466
33
333
500
33
266
533
33
233
583
33
200
600
33
300
600
33
266
667
33
333
667
66
200
400
66
200
400
66
266
400
66
266
400
66
200
500
66
333
500
66
266
533
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
73