MPC8349VVALF View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVALF

PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

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I2C

Table 39. I2C AC Electrical Specifications (continued)

Parameter

Symbol1

Min

Max

Unit

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

tI2CR

20 + 0.1 Cb4

300

ns

tI2CF

20 + 0.1 Cb4

300

ns

Setup time for STOP condition

tI2PVKH

0.6

—

μs

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs

Noise margin at the LOW level for each connected device (including

VNL

0.1 × OVDD

—

V

hysteresis)

Noise margin at the HIGH level for each connected device (including

VNH

0.2 × OVDD

—

V

hysteresis)

Notes:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with

respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H)

state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S)

goes invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C

timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. MPC8349E provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

3. The maximum tI2DVKH must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

Figure 30 provides the AC test load for the I2C.

Output

Z0 = 50 Ω

RL = 50 Ω

OVDD/2

Figure 30. I2C AC Test Load

Figure 31 shows the AC timing diagram for the I2C bus.

SDA

SCL

S

tI2CF

tI2CL

tI2SXKL

tI2DVKH

tI2SXKL

tI2KHKL

tI2CR

tI2CF

tI2DXKL

tI2CH

tI2SVKH

tI2PVKH

Sr

P

S

Figure 31. I2C Bus AC Timing Diagram

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

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