MPC8541CPXAJD View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8541CPXAJD
Freescale Semiconductor
'MPC8541CPXAJD' PDF : 84 Pages View PDF
Local Bus
9.2 Local Bus AC Electrical Specifications
Table 30 describes the general timing parameters of the local bus interface of the MPC8541E with the DLL
enabled.
Table 30. Local Bus General Timing Parameters—DLL Enabled
Parameter
Configuration 7
Symbol 1 Min
Max
Unit Notes
Local bus cycle time
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
tLBK
6.0
—
tLBKSKEW
—
150
tLBIVKH1
1.8
—
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
tLBIVKH2
1.7
—
tLBIXKH1
0.5
—
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
tLBIXKH2
1.0
—
tLBOTOT
1.5
—
Local bus clock to output valid (except
LWE[0:1] = 00
tLBKHOV1
—
2.3
LAD/LDP and LALE)
LWE[0:1] = 11 (default)
3.8
Local bus clock to data valid for LAD/LDP
LWE[0:1] = 00
tLBKHOV2
—
2.5
LWE[0:1] = 11 (default)
4.0
Local bus clock to address valid for LAD
LWE[0:1] = 00
tLBKHOV3
—
2.6
LWE[0:1] = 11 (default)
4.1
Output hold from local bus clock (except
LWE[0:1] = 00
tLBKHOX1
0.7
—
LAD/LDP and LALE)
LWE[0:1] = 11 (default)
1.6
Output hold from local bus clock for
LAD/LDP
LWE[0:1] = 00
tLBKHOX2
0.7
—
LWE[0:1] = 11 (default)
1.6
Local bus clock to output high Impedance
LWE[0:1] = 00
tLBKHOZ1
—
2.8
(except LAD/LDP and LALE)
LWE[0:1] = 11 (default)
4.2
ns
2
ps
7, 9
ns
3, 4, 8
ns
3, 4
ns
3, 4, 8
ns
3, 4
ns
6
ns
3, 8
ns
3, 8
ns
3, 8
ns
3, 8
ns
3, 8
ns
5, 9
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
33
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