MSM514262-10JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM514262-10JS' PDF : 45 Pages View PDF
¡ Semiconductor
MSM514262
Write Mask Data/Data Input and Output : W1/IO1 - W4/IO4
W1/IO1 - W4/IO4 have the functions of both Input/Output and a control input signal. As the
standard DRAM’s I/O pins, input data on the W1/IO1 - W4/IO4 are written into the RAM port
during the write cycle. The input data is latched at the falling edge of either CAS or WB/WE,
whichever occurs later. The RAM data out buffers, which will output read data from the W1/
IO1 - W4/IO4 pins, becomes low impedance state after the specified access times from RAS,
CAS, DT/OE and column address are satisfied and the output data will remain valid as long
as CAS and DT/OE are kept “low”. The outputs will return to the high impedance state at the
rising edge of either CAS or DT/OE, whichever occurs earlier.
In addition to the conventional I/O function, the W1/IO1 - W4/IO4 have the function to set the
mask data, which select mask input pins out of four input pins, W1/IO1 - W4/IO4, at the falling
edge of RAS. Data is written to the DRAM on data lines where the Write-mask data is a logic
“1”. The write-mask data is valid for only one cycle.
Serial Clock : SC
SC is a main serial cycle control input signal. All operations of SAM port are synchronized with
the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In a
serial read, the output data becomes valid on the SIO pins after the maximum specified serial
access time tSCA from the rising edge of SC.
The SC also increments the 9 bits serial pointer which is used to select the SAM address. The
pointer address is incremented in a wrap-around mode to select sequential locations after the
setting location which is determined by the column address in the read transfer cycle. When the
pointer reaches the most significant address location (decimal 511), the next SC clock will place
it at the least significant address location (decimal 0).
The SC must be held data constant VIH or VIL level during read/pseudo write/write-transfer
operations and should not be clocked while the SAM port is in the standby mode to prevent the
SAM pointer from being incremented.
Serial Enable : SE
The SE is a serial access enable control and serial read/write control signal. In a serial read cycle,
SE is used as an output control. In a serial write cycle, SE is used as write enable control. When
SE is “high”, serial access is disable, however, the serial address pointer location is still
incremented when SC is clocked even when SE is “high”.
Special Function Input : DSF
The DSF is latched at the falling edge of RAS and CAS and allows for the selection of several
RAM port and transfer operating modes. In addition to the conventional multiport DRAM, the
special function consisting of flash write, block write, load/read resister and read/write
transfer can be invoked.
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