MSM514262-10JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM514262-10JS' PDF : 45 Pages View PDF
¡ Semiconductor
MSM514262
RAM PORT OPERATION
Fast Page Mode
Fast page mode allows data to be transferred into or out of multiple column locations of the
same row by performing multiple CAS cycle during a signal active for a period up to 100m
seconds. For the initial fast page mode access, the output data is valid after the specified access
times from RAS, CAS, column address and DT/OE.
For all subsequent fast page mode read operations, the output data is valid after the specified
access times from CAS, column address and DT/OE. When the write-per bit function is enable,
the mask data latched at the falling edge of RAS is maintained throughout the fast page mode
write or read or read modify write cycle.
RAS Only Refresh
The data in the DRAM requires periodic refreshing to prevent data loss. Refreshing is
accomplished by performing a memory cycle at each of the 512 rows in the DRAM array within
the specified 8ms refresh period.
Although any normal memory cycle will perform the refresh operation, this function is most
easily accomplished with “RAS-only” cycle.
CAS before RAS Refresh
The MSM514262 also offers an internal refresh function. When CAS is held “low” for a specified
period (tCSR) before RAS goes “low”, an internal refresh address counter and on-chip refresh control
clock generators are enable refresh operation take place.
When the refresh operation is completed, the internal refresh address counter is automatically
incremented in preparation for the next CAS before RAS cycle. For successive CAS before RAS
refresh cycle, CAS can remain “low” while cycling RAS.
Hidden Refresh
A hidden refresh is a CAS before RAS refresh performed by holding CAS “low” from a previous read
cycle. This allows for the output data from the previous memory cycle to remain valid while
performing a refresh.
The internal refresh address counter provides the address and the refresh is accomplished by cycling
RAS after the specified RAS precharge period.
Write-per-Bit Function
The write per bit selectively controls the internal write enable circuits of the RAM port. Write per bit
is enabled when WB/WE held “low at the falling edge of RAS in a random write operation. Also,
at the falling edge of RAS, the mask data on the Wi/IOi pins are latched into a write mask register.
The write mask data must be presented at the Wi/IOi pins at every falling edge of RAS. A “0” on any
of the Wi/IOi pins will disable the corresponding write circuits and new data will not be written into
the RAM. A “1” on any of Wi/IOi pins will enable the corresponding write circuits and new data will
be written into the RAM.
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