MSM514262-10JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM514262-10JS' PDF : 45 Pages View PDF
¡ Semiconductor
MSM514262
Load / Read Color Register
The MSM514262 is provided with an on-chip 4 bits color register for use during the flash write
or block write operation. Each bit of the color register corresponds to one of the DRAM I/O
blocks.
The load color register cycle is initiated by holding CAS, WB/WE, DT/OE and DSF “high” at
the falling edge of RAS. The data presented on the Wi/IOi lines is subsequently latched into the
color register at the falling edge of either CAS or WB/WE whichever occurs later.
The read color register cycle is activated by holding CAS, WB/WE, DT/OE and DSF “high” at
the falling edge of RAS and by holding WB/WE “high” at the falling edge of CAS and
throughout the remainder of the cycle. The data in the color register becomes valid on the Wi/
IOi lines after the specified access times from RAS and DT/OE are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Flash Write
Flash write allows for the data in the color register to be written into all the memory locations
of a selected row.
Each bit of the color register corresponds to the DRAM I/O blocks and the flash write operation
can be selectively controlled on an I/O basis in the same manner as the write per bit operation.
A flash write cycle is performed by holding CAS “high” WB/WE “low” and DSF “high” at the
falling edge of RAS. The mask data must also be provided on the Wi/IOi lines at the falling edge
of RAS in order to enable the flash write operation for selected I/O blocks.
Block Write
Block write allows for the data in the color register to be written into 4 consecutive column
address locations starting from a selected row. The block write operation can be selectively
controlled on an I/O basis and a column mask capability is also available.
Block write cycle is performed by holding CAS, DT/OE “high” and DSF “low” at the falling
edge of RAS and by holding DSF “high” at the falling edge of CAS. The state of the WB/WE
input at the falling edge of RAS determines whether or not the I/O data mask is enabled (WB/
WE must be “low” to enable the I/O data mask or “high” to disable mask). At the falling edge
of RAS, a valid row address and I/O mask data are also specified. At the falling edge of CAS,
the starting column address location and column address data mast be provided. During a
block write cycle, the 2 least significant column address locations (A0C, A1C) are internally
controlled and only the 7 most significant column addresses (A2C - A8C) are latched at the
falling edge of CAS.
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