MSM548263-80JS View Datasheet(PDF) - Oki Electric Industry
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MFG CO.
'MSM548263-80JS' PDF : 40 Pages View PDF
¡ Semiconductor
MSM548263
Split Data Transfer and QSF
The MSM548263 features a bidirectional split data transfer capability between the RAM and
SAM. During split data transfer operation, the serial register is split into two halves which can
be controlled independently. Split read or split write transfer operation can be performed to or
from one half of the serial register, while serial data can be shifted into or out of the other half of
the serial register. The most significant column address location (A8C) is controlled internally to
determines which half of the serial register will be reloaded from the RAM. QSF is an output
which indicates which half of the serial register is in an active state. QSF changes state when the
last SC clock is applied to active split SAM.
Split Read Transfer: RAS falling edge --- CAS = WE = DSF = "H", TRG = "L"
The MSM548263 supports two types of split register operation.
#1 Normal split register operation
#2 Boundary split register operation using programmable SAM stops described later.
Normal split read transfer consists of loading 256 words by 8 bits of data from a selected row of
the split RAM into the corresponding non-active split SAM register. Serial data can be shifted out
from the other half of the split SAM register simultaneously. During split read transfer operation,
the RAM port input clocks do not have to be synchronized with the serial clock SC, thus
eliminating timing restrictions as in the case of real time read transfers. A split read transfer can
be performed after a delay of tSTS from the change of state of the QSF output is satisfied.
Conventional (non-split) read transfer operation must precede split read transfer cycles.
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