MSM548263-80JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM548263-80JS' PDF : 40 Pages View PDF
¡ Semiconductor
MSM548263
SAM Stop Set Cycle (CBRS): RAS falling edge --- CAS = "L", WE = "L", DSF = "H"
SAM Stop location data (boundaries) are latched from address inputs at the falling edge of RAS.
To determine the boundary A4 - A7 are used, and A0 - A3, and A8 are ignored.
Once the CBRS is executed, the programmable SAM stop operation continues until CBRR.
Number of Stop Points
1
2
4
8
16
SAM Stop Boundary Table
Address
A4 A5 A6 A7
1
1
1
1
1
1
1
0
1
1
0
X
1
0
X
X
0
X
X
X
Size of Partition
256
128
64
32
16
Register Reset Cycle (CBRR): RAS falling edge --- CAS = "L", WE = "H", DSF = "L"
A CBRR can reset the programmable SAM stop operation, and persistent mask write operation.
The CBRR will take effect immediately; it doesn’t require a split transfer cycle.
POWER UP
Power must be applied to the RAS and TRG input signals to pull them "high" before, or at the
same time as, the VCC supply is turned on. After power-up, a pause of 200 ms minimum is
required with RAS and TRG held "high". After the pause, a minimum of 8 RAS and 8 SC dummy
cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer
operations can begin. During the initialization period, the TRG signal must be held "high". If the
internal refresh counter is used, a minimum 8 CAS before RAS cycles are required instead of 8
RAS cycles.
(NOTE) INITIAL STATE AFTER POWER UP
The initial state can not be guaranteed for various power up conditions and input signal levels.
Therefore, it is recommended that the initial state be set (ex. Perform a CBRR cycle to select Non
Persistent Write-per-bit mode) after the initialization of the device is performed and before valid
operations begin.
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