MSM548263-80JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM548263-80JS' PDF : 40 Pages View PDF
¡ Semiconductor
MSM548263
Masked Split Write Transfer: RAS falling edge --- CAS = DSF = "H", TRG = WE = "L"
Split write transfer consists of loading 256 words by 8 bits of data from the non-active split SAM
register into a selected row of the corresponding split RAM. Serial data can be shifted into the
other half of the split SAM register simultaneously. During split write transfer operation, the
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing
for real time transfer. This operation is the same as a mask write operation in RAM, so new and
persistent mode can be supported.
A split write transfer can be performed after a delay of tSTS from the change of state of the QSF
output is satisfied.
A masked write transfer operation must precede split write transfer. The purpose is to switch the
SAM port from output mode to input mode, and to set the initial TAP location prior to split write
transfer operations.
Programmable SAM Stops in Split Transfer Cycle
The MSM548263 has a boundary split register operation using programmable stops. If a CBRS
cycle has been performed, the split transfer cycle performs the boundary operation.
Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a
SAM location at which the access will change from one half of the SAM to the other half (at the
TAP address).
TAP1
0
Lower SAM
TAP3
255 256
Upper SAM
TAP2
511
S.T. (TAP2)
Figure 2. Example of Boundary Split Register
S.T. (TAP3)
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