1Semiconductor
PEDL66577-01
MSM66577 Family
Slave mode (Clock synchronous serial port)
Parameter
Cycle time
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Symbol
tcyc
tSCKC
tSTMXS
tSTMXH
tSRMXS
tSRMXH
Condition
fOSC = 30 MHz
CL = 50 pF
tcyc
CPUCLK
(VDD = 4.5 to 5.5 V, Ta = –30 to +70°C)
Min.
Max.
Unit
33.3
—
6 tcyc
—
3 tφ – 15
—
ns
6 tφ – 10
—
13
—
3
—
Note: tφ = tcyc/2
SIOCK
SDOUT
(SIOO)
SDIN
(SIOI)
tSTMXH
tSCKC
tSTMXS
tSRMXS
tSRMXH
Measurement points for AC timing (except the serial port)
VDD
2.0 V
2.0 V
0V
0.8 V
0.8 V
Measurement points for AC timing (the serial port)
VDD
0.8VDD
0V
0.2VDD
0.8VDD
0.2VDD
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