MSM82C37B-5VJS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM82C37B-5VJS' PDF : 34 Pages View PDF
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Command Register
This 8-bit write-only register prescribes DMA operations for all MSM82C37B-5 channels. An
outline of all bits is given in Figure 3. When the controller is disabled by setting D B2, there is
no HRQ output even if DMA request is active.
DREQ and DACK signals may be active high or active low by setting D B6 and DB7.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0: Memory-Memory Transfer Disabled
1: Memory-Memory Transfer Enabled
0: Channel 0 Address Hold Disabled
1: Channel 0 Address Hold Enabled
(Invalid when DB0 = "0")
0: Controller Enabled
1: Controller Disabled
0: Normal Timing
1: Compressed Timing
(Invalid when DB0 = "1")
0: Fixed Priority
1: Rotating Priority
0: Normal Write Pulse Width
1: Extended Write Pulse Width
0: DREQ Sense Active "H"
1: DREQ Sense Active "L"
0: DACK Sense Active "L"
1: DACK Sense Active "H"
Figure 3 Command Register
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