MSM82C37B-5VJS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM82C37B-5VJS' PDF : 34 Pages View PDF
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
PROGRAMMING
The MSM82C37B-5 is switched to programming status when the HLDA input and CS are both
at low level. In this state, IOR is changed to low level with IOW held at high level to enable
reading by the CPU, or else IOW is changed to low level while IOR is held at high level to enable
writing by the CPU. A list of command codes for reading from the MSM82C37B-5 is given in
Table 2, and a list of command codes for writing in the MSM82C37B-5 is given Table 3.
Note: If a DMA transfer request is received from an I/O device during MSM82C37B-
5 programming, that DMA transfer may be commenced to prevent proper programming.
To prevent this interference, the DMA channel must be masked, or the controller
disabled by the command register, or the system set to as to prevent DREQ becoming
active during the programming.
Table 2 List of MSM82C37B-5 Read Commands
Internal
CS IOR A3 A2 A1 A0 First/Last
Flip/Flop
000000
0
000000
1
000001
0
000001
1
000010
0
000010
1
000011
0
000011
1
000100
0
000100
1
000101
0
000101
1
000110
0
000110
1
000111
0
000111
1
001000
¥
001101
¥
0 0 Other Combinations
¥
Read Out Data
Channel 0
Current Address
Register
Current Word Count
Register
Channel 1
Current Address
Register
Current Word Count
Register
Channel 2
Current Address
Register
Current Word Count
Register
Channel 3
Current Address
Register
Current Word Count
Register
Status Register
Temporary Register
Output Data Invalid
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
27/33
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