¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Mask Register
This register is used in disabling and enabling of DMA transfers in each channel. Each channel
includes a corresponding mask bit in the mask register, and each bit is set when the TC is reached
if not in autoinitialize mode. This mask register can be set in two different ways.
The method for setting/resetting the register for each channel is outlined in Figure 6(a), while
the method for setting/resetting the register for all channels at once is outlined in Figure 6(b).
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00: Channel 0 Selected
01: Channel 1 Selected
10: Channel 2 Selected
11: Channel 3 Selected
0: Mask Bit Cleared
1: Mask Bit Set
Not Used
(a) Single Mask Register (Setting/Resetting for Each Channel)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0: Channel 0 Mask Bit Cleared
1: Channel 0 Mask Bit Set
0: Channel 1 Mask Bit Cleared
1: Channel 1 Mask Bit Set
0: Channel 2 Mask Bit Cleared
1: Channel 2 Mask Bit Set
0: Channel 3 Mask Bit Cleared
1: Channel 3 Mask Bit Set
Not Used
(b) All Mask Register (Setting/Resetting of All Channels at Once)
Figure 6 Mask Register
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