MSM82C59A-2JS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
MFG CO.
'MSM82C59A-2JS' PDF : 28 Pages View PDF
¡ Semiconductor
Contents of the Second Interrupt vector byte
IR
Interval = 4
D7
D6
D5
D4
D3
7
A7
A6
A5
1
1
6
A7
A6
A5
1
1
5
A7
A6
A5
1
0
4
A7
A6
A5
1
0
3
A7
A6
A5
0
1
2
A7
A6
A5
0
1
1
A7
A6
A5
0
0
0
A7
A6
A5
0
0
IR
Interval = 8
D7
D6
D5
D4
D3
7
A7
A6
1
1
1
6
A7
A6
1
1
0
5
A7
A6
1
0
1
4
A7
A6
1
0
0
3
A7
A6
0
1
1
2
A7
A6
0
1
0
1
A7
A6
0
0
1
0
A7
A6
0
0
0
MSM82C59A-2RS/GS/JS
D2
D1
D0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The higher address of the interrupt service routine programmed by the second bytes (A8 -
A15) of the initialization sequence is released to the data bus.
Contents of the Third Interrupt Vector Byte
D7 D6 D5 D4 D3 D2 D1 D0
A15 A14 A13 A12 A11 A10 A9 A8
86 Mode (MSM80C86A-10/88A-10)
Apart from the two interrupt acknowledge cycles and the absence of a CALL operation
code, the 86 mode is the same as the 85 mode. The first INTA cycle freezes interrupt status
to resolve the priority internally in the same way as in 85 mode. When the device is used
as a master, an interrupt code is issued to the cascade line at the end of the INTA pulse.
During this first cycle, the data bus buffer is kept at high impedance without any data to
the CPU. During the second INTA cycle, the MSM82C59A-2 sends a byte of interrupt code
to the CPU. Note that in 86 mode, the Address Interval (ADI) control status is ignored and
A5-A10 is not used.
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