MT28C3212P2FL-10B View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28C3212P2FL-10B' PDF : 47 Pages View PDF
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
SRAM OPERATING MODES
SRAM READ ARRAY
The operational state of the SRAM is determined by
S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as
indicated in the Truth Table. To perform an SRAM
READ operation, S_CE1#, and S_OE#, must be at VIL,
and S_CE2 and S_WE# must be at VIH. When in this
state, S_UB# and S_LB# control whether the lower byte
is read (S_UB# VIH, S_LB# VIL), the upper byte is read
(S_UB# VIL, S_LB# VIH), both upper and lower bytes are
read (S_UB# VIL, S_LB# VIL), or neither are read (S_UB#
VIH, S_LB# VIH) and the device is in a standby state.
While performing an SRAM READ operation, cur-
rent consumption may be reduced by reading within a
16-word page. This is done by holding S_CE1# and
S_OE# at VIL, S_WE# and S_CE2 at VIH, and toggling
addresses A0-A3. S_UB# and S_LB# control the data
width as described above.
SRAM WRITE ARRAY
In order to perform an SRAM WRITE operation,
S_CE1# and S_WE# must be at VIL, and S_CE2 and
S_OE# must be at VIH. When in this state, S_UB# and
S_LB# control whether the lower byte is written (S_UB#
VIH, S_LB# VIL), the upper byte is written (S_UB# VIL,
S_LB# VIH), both upper and lower bytes are written
(S_UB# VIL, S_LB# VIL), or neither are written (S_UB#
VIH, S_LB# VIH) and the device is in a standby state.
SRAM FUNCTIONAL BLOCK DIAGRAM
A0–A3
WORD
ADDRESS
DECODE
LOGIC
A4–A16
PAGE
ADDRESS
DECODE
LOGIC
8K-PAGE
x16 WORD
x16 BIT
RAM ARRAY
WORD
MUX
INPUT/
OUTPUT
MUX
AND
BUFFERS
DQ0–DQ7
DQ8–DQ15
S_CE1#
S_CE2
S_WE#
S_OE#
S_UB#
S_LB#
CONTROL
LOGIC
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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