MT28F128J3FS-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F128J3FS-12F' PDF : 52 Pages View PDF
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 4
WRITE-to-BUFFER Flowchart
Start
Set Timeout
Issue
WRITE-to-BUFFER
No
Command E8h,
Block Address
Read Extended
Status Register
XSR7 =
0
WRITE-to-
BUFFER Timeout?
1
Write Word or
Byte Count N,
Block Address
Write Buffer Data,
Start Address
X=0
Yes
Check
X = N?
No
Yes
Abort
Yes
WRITE-to-BUFFER
Command?
Write to Another
Block Address
Yes
No
Write Next Buffer
Data, Device Address
Write to Buffer
Aborted
X=X+1
Program Buffer to
Flash Confirm D0h
Yes
Another
WRITE-to-BUFFER
?
No
Read Status Register
1
0
SR7 =
1
Full Status
Check if Desired
Programming
Complete
Issue
READ STATUS
Command
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE-to-
BUFFER
Data = E8h
Block Address
READ
XSR7 = Valid
Addr = Block Address
STANDBY
WRITE1, 2
WRITE3, 4
WRITE5, 6
Check XSR7
1 = Write Buffer Available
0 = Write Buffer Not Available
Data = N = Word/Byte Count
N = 0 Corresponds to Count = 1
Addr = Block Address
Data = Write Buffer Data
Addr = Device Start Address
Data = Write Buffer Data
Addr = Device Address
WRITE
READ7
Program
Data = D0h
Buffer to
Addr = Block Address
Flash Confirm
Status register data with the
device enabled, OE# LOW
updates SR
Addr = Block Address
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation
to reset the device to read array mode.
NOTE:
1. Byte or word count values on DQ0–DQ7 are loaded into the count register. Count ranges on this device for byte mode
are n = 00h to 1Fh and for word mode are n = 0000h to 000Fh.
2. The device now outputs the status register when read (XSR is no longer available).
3. Write buffer contents will be programmed at the device start address or destination Flash address.
4. Align the start address on a write buffer boundary for maximum programming performance (i.e., A4–A0 of the start
address = 0).
5. The device aborts the WRITE-to-BUFFER command if the current address is outside of the original block address.
6. The status register indicates an “improper command sequence” if the WRITE-to-BUFFER command is aborted. Follow
this with a CLEAR STATUS REGISTER command.
7. Toggling OE# (LOW to HIGH to LOW) updates the status register. This can be done in place of issuing the READ STATUS
REGISTER command.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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