Figure 5
Byte/Word Program Flowchart
Start
Write 40h,
Address
Write Data and
Address
Read Status
Register
0
SR7 =
1
Full Status
Check if Desired
Byte/Word
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (see above)
1
SR3 =
0
1
SR1 =
0
1
SR4 =
0
Byte/Word
Program Successful
Voltage Range Error
Device Protect Error
Programming Error
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
BUS
OPERATION COMMAND COMMENTS
WRITE
SETUP BYTE/ Data = 40h
WORD
Addr = Location to be
PROGRAM
Programmed
WRITE
BYTE/
WORD
PROGRAM
Data = Data to be
Programmed
Addr = Location to be
Programmed
READ
Status Register Data
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Toggling OE# (LOW to HIGH to LOW) updates the status
register. This can be done in place of issuing the READ
STATUS REGISTER command. Repeat for subsequent
programming operations.
After each program operation or after a sequence of
programming operations, an SR full status check can be
done.
Write FFh after the last program operation to place the
device in read array mode.
BUS
OPERATION COMMAND
STANDBY
STANDBY
STANDBY
COMMENTS
Check SR3
1 = Programming to
Voltage Error Detect
Check SR1
1 = Device Protect Detect
RP# = VIH, Block Lock Bit is
Set
Only required for systems
implemeting lock bit
configuration
Check SR4
1 = Programming Error
Toggling OE# (LOW to HIGH to LOW) updates the status
register. This can be done in place of issuing the READ
STATUS REGISTER command. Repeat for subsequent
programming operations.
SR4, SR3, and SR1 are only cleared by the CLEAR STATUS
REGISTER command in cases where multiple locations are
programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
29
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©2002, Micron Technology, Inc.