MT28F128J3FS-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F128J3FS-12F' PDF : 52 Pages View PDF
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
AC CHARACTERISTICS – WRITE OPERATIONS
(Notes: 1, 2, 3); Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
AC CHARACTERISTICS
PARAMETER
RP# High Recovery to WE# (CEx) Going LOW
CEx (WE#) LOW to WE# (CEx) Going LOW
Write Pulse Width
Data Setup to WE# (CEx) Going HIGH
Address Setup to WE# (CEx) Going HIGH
CEx (WE#) Hold from WE# (CEx) HIGH
Data Hold from WE# (CEx) HIGH
Address Hold from WE# (CEx) HIGH
Write Pulse Width HIGH
VPEN Setup to WE# (CEx) Going HIGH
Write Recovery Before Read
WE# (CEx) HIGH to STS Going LOW
VPEN Hold from Valid SRD, STS Going HIGH
WE# (CEx) HIGH to Status Register Busy
SYMBOL
tRS
tCS (tWS)
tWP (tCP)
tDS
tAS
tCH (tWH)
tDH
tAH
tWPH (tCPH)
tVPS
tWR
tSTS
tVPH
tWB
-11/-12/-15
MIN
MAX
1
0
70
50
55
0
0
0
30
0
35
200
0
200
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
5
5
6
6
7
4
8
9
4, 9, 10
4
NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first edge
of CE0, CE1, or CE2 that disables the device.
2. Read timing characteristics during BLOCK ERASE, PROGRAM, and LOCK BIT CONFIGURATION operations are the same as
during READ-only operations. Refer to AC Characteristics – Read-Only Operations.
3. A WRITE operation can be initiated and terminated with either CEX or WE#.
4. Sampled, not 100% tested.
5. Write pulse width (tWP) is defined from CEx or WE# going LOW (whichever goes LOW last) to CEx or WE# going HIGH
(whichever goes HIGH first).
6. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock bit configuration.
7. Write pulse width HIGH (t WPH) is defined from CEx or WE# going HIGH (whichever goes HIGH first) to CEx or WE# going
LOW (whichever goes LOW first).
8. For array access, tAA is required in addition to tWR for any accesses after a WRITE.
9. STS timings are based on STS configured in its RY/BY# default mode.
10. VPEN should be held at VPENH until determination of block erase, program, or lock bit configuration success (SR1/3/4/5 =
0).
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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