MT28F320J3RG-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F320J3RG-12F' PDF : 52 Pages View PDF
Figure 9
SET BLOCK LOCK BITS Flowchart
Start
Write 60h,
Block Address
Write 01h,
Block Address
Read Status
Register
0
SR7 =
1
Full Status
Check if Desired
SET BLOCK LOCK BITs
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (see above)
1
SR3 =
0
1
SR4,5 =
0
1
SR4 =
0
SET BLOCK LOCK BITS
Successful
Voltage Range Error
Command Sequence
Error
SET BLOCK LOCK BITS
Error
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
BUS
OPERATION COMMAND COMMENTS
WRITE
SET BLOCK Data = 60h
LOCK BITS Addr = Block Address
SETUP
WRITE
SET BLOCK Data = 01h
LOCK BITS Addr = Block Address
CONFIRM
READ
Status Register Data
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Repeat for subsequent lock bit operations.
Full status check can be done after each lock bit set
operation or after a sequence of lock bit set operations
Write FFh after the last lock bit set operation to place
device in read array mode.
BUS
OPERATION COMMAND
STANDBY
STANDBY
STANDBY
COMMENTS
Check SR3
1 = Programming Voltage
Error Detect
Check SR4, SR5
Both 1 = Command
Sequence Error
Check SR4
1 = Set Block Lock Bits
Error
SR5, SR4, and SR3 are only cleared by the CLEAR STATUS
REGISTER command in cases where multiple lock bits are set
before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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