MT28F320J3RG-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F320J3RG-12F' PDF : 52 Pages View PDF
DESIGN CONSIDERATIONS
FIVE-LINE OUTPUT CONTROL
Micron provides five control inputs (CE0, CE1, CE2,
OE#, and RP#) to accommodate multiple memory con-
nections in large memory arrays. This control provides
the lowest possible memory power dissipation and en-
sures that data bus contention does not occur.
To efficiently use these control inputs, an address
decoder should enable the device (see Table 2) while
OE# is connected to all memory devices and the
system’s READ# control line. This ensures that only
selected memory devices have active outputs while
deselected memory devices are in standby mode. Dur-
ing system power transitions, RP# should be connected
to the system POWERGOOD signal to prevent unin-
tended writes. POWERGOOD should also toggle dur-
ing system reset.
STS AND BLOCK ERASE, PROGRAM, AND
LOCK BIT CONFIGURATION
POLLING
As an open drain output, STS should be connected
to VCCQ by a pull-up resistor to provide a hardware
method of detecting block erase, program, and lock bit
configuration completion. It is recommended that a
2.5KΩ resistor be used between STS# and VCCQ. In de-
fault mode, it transitions LOW after block erase, pro-
gram, or lock bit configuration commands and returns
to High-Z when the ISM has finished executing the
internal algorithm. See the CONFIGURATION com-
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
mand for alternate configurations of the STS pin. STS
can be connected to an interrupt input of the system
CPU or controller. STS is active at all times. In default
mode, it is also High-Z when the device is in block erase
suspend (with programming inactive), program sus-
pend, or reset/power-down mode.
POWER SUPPLY DECOUPLING
Device decoupling is required for Flash memory
power switching characteristics. There are three sup-
ply current issues to consider: standby current levels,
active current levels, and transient peaks produced by
falling and rising edges of CEx and OE#. Transient cur-
rent magnitudes depend on the device outputs’ ca-
pacitive and inductive loading. Two-line control and
proper decoupling capacitor selection suppresses tran-
sient voltage peaks. Because Micron Q-Flash memory
devices draw their power from three VCC pins (these
devices do not include a VPP pin), it is recommended
that systems without separate power and ground
planes attach a 0.1µF ceramic capacitor between each
of the device’s three VCC pins (this includes VCCQ) and
GND. These high-frequency, low-inductance capaci-
tors should be placed as close as possible to package
leads on each Micron Q-Flash memory device. Addi-
tionally, for every eight devices, a 4.7µF electrolytic
capacitor should be placed between VCC and GND at
the array’s power supply connection.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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