MT28F320J3RG-12F View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F320J3RG-12F' PDF : 52 Pages View PDF
Figure 10
CLEAR BLOCK LOCK BITS Flowchart
Start
Write 60h
Write D0h
Read Status
Register
0
SR7 =
1
Full Status
Check if Desired
CLEAR BLOCK LOCK
BITS Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (see above)
1
SR3 =
0
1
SR4,5 =
0
1
SR5 =
0
CLEAR BLOCK LOCK
BITS Successful
Voltage Range Error
Command Sequence
Error
CLEAR BLOCK LOCK
BITS Error
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
BUS
OPERATION COMMAND COMMENTS
WRITE
CLEAR
Data = 60h
BLOCK LOCK Addr = X
BITS SETUP
WRITE
CLEAR BLOCK Data = D0h
LOCK BITS Addr = X
or CONFIRM
READ
Status Register Data
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Write FFh after the CLEAR BLOCK LOCK BITS operation to
place device in read array mode.
BUS
OPERATION COMMAND COMMENTS
STANDBY
Check SR3
1 = Programming Voltage
Error Detect
STANDBY
Check SR4, 5
Both 1 = Command
Sequence Error
STANDBY
Check SR5
1 = Clear Block Lock Bits
Error
SR5, SR4, and SR3 are only cleared by the CLEAR STATUS
REGISTER command.
If an error is detected, clear the status register before
attempting retry or other error recovery.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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