MT46V2M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V2M32' PDF : 65 Pages View PDF
64Mb: x32
DDR SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n – COMMAND TO BANK m
(Notes: 1-9; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
HXXX
L HHH
Idle
XXXX
Row
L L HH
Activating,
LHLH
Active, or
LHL L
Precharging L L H L
Read
L L HH
(Auto-
LHLH
Precharge
LHL L
Disabled)
L LHL
Write
L L HH
(Auto-
LHLH
Precharge
LHL L
Disabled)
L LHL
Read
L L HH
(With Auto- L H L H
Precharge)
LHL L
L LHL
Write
L L HH
(With Auto- L H L H
Precharge)
LHL L
L LHL
COMMAND/ACTION
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
NOTES
7
7
7
7, 9
7, 8
7
7, 3a
7, 9, 3a
7, 3a
7, 3a
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read with Auto
Precharge Enabled: See following text - 3a
Write with Auto
Precharge Enabled: See following text - 3a
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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