MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Operations
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 24.
Figure 26: Power-Down
CLK
tCKS
((
))
((
))
> tCKS
CKE
((
))
((
COMMAND
NOP
))
((
NOP
))
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
ACTIVE
tRCD
tRAS
tRC
DON’T CARE
Deep Power-Down
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data in the memory array will not be
retained once deep power-down mode is executed. Deep power-down mode is entered
by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the
rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep power-
down.
To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of Deep Power-
Down mode, at least 200µs of valid clocks with either NOP or COMMAND INHIBIT
commands are applied to the command bus, followed by a full Mobile SDRAM initializa-
tion sequence, is required.
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 27 and Figure 28 on page 37.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the MR to a logic 1. In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the programmed BL. READ
commands access columns according to the programmed BL and sequence, just as in
the normal mode of operation (M9 = 0).
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
35
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©2006 Micron Technology, Inc. All rights reserved.
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