MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Operations
Concurrent Auto Precharge
An access command (READ or WRITE) to a second bank while an access command with
auto precharge enabled on a first bank is executing is not allowed by SDRAM, unless the
SDRAM supports concurrent auto precharge. Micron SDRAM support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined in the “READ
with Auto Precharge” and “WRITE with Auto Precharge” sections.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (see Figure 29 on page 37).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (see Figure 30 on page 38).
Figure 27: Clock Suspend During WRITE Burst
T0
T1
T2
T3
CLK
T4
T5
CKE
INTERNAL
CLOCK
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
BANK,
COL n
DIN
DIN
n
DIN
n+1
DIN
n+2
DON’T CARE
Note: For this example, BL = 4 or greater, and DM is LOW.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
36
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©2006 Micron Technology, Inc. All rights reserved.
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