MT48LC128M4A2P-7EITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7EITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Notes
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns for all inputs. VIH overshoot for pin A12 is limited to VDDQ + 1V for
a pulse width ≤ 3ns, and the pulse width cannot be greater than one-third of the cycle
rate.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after
the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -75, CL = 3, tCK = 7.5ns; for -7E, CL = 2, tCK = 7.5ns.
30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
48
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