MT48LC128M4A2P-7EITC View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT48LC128M4A2P-7EITC

Synchronous DRAM

Micron Technology 

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512Mb: x4, x8, x16 SDRAM

Timing Diagrams

Timing Diagrams

Figure 33: Initialize and Load Mode Register

CK

CKE

COMMAND

T0

((

))

tCKS tCKH

T1

tCK

Tn + 1

((

))

((

tCH

))

((

((

))

))

((

((

))

))

tCMS tCMH tCMS tCMH tCMS tCMH

((

))

((

NOP

))

((

))

PRECHARGE ( (

))

AUTO

REFRESH

((

))

((

))

((

))

((

))

NOP( ( NOP

))

((

DQM/

))

DQML, DQMH

((

))

((

((

))

))

((

((

))

))

((

A0–A9, ) )

((

))

A11, A12 ( (

))

((

))

((

A10

))

((

))

ALL BANKS ( (

))

((

SINGLE BANK ) )

((

BA0, BA1 ) )

((

))

DQ

((

))

T = 100µs

MIN

High-Z

((

ALL

))

BANKS ( (

))

((

))

tRP

((

))

((

))

((

))

((

))

((

))

((

))

tRFC

To + 1

tCL

((

))

((

))

((

))

AUTO

REFRESH

((

))

NOP( ( NOP

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

tRFC

Tp + 1

Tp + 2

LOAD MODE

REGISTER

NOP

tAS tAH 5

CODE

tAS tAH

CODE

tMRD

Tp + 3

ACTIVE

ROW

ROW

BANK

Power-up:

VDD and

CLK stable

Precharge

all banks

AUTO REFRESH

AUTO REFRESH

Program mode register 2, 3, 4

Don’t Care

Notes:

1. If CS is HIGH at clock high time, all commands applied are NOP.

2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

3. JEDEC and PC100 specify three clocks.

4. Outputs are guaranteed High-Z after command is issued.

5. A12 should be a LOW at Tp + 1.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

49

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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