MT48LC128M4A2P-7ELITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7ELITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 41: Single READ – With Auto Precharge
T0
CLK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
T1
tCK
NOP
DQM/
DQML, DQMH
A0–A9, A12
tAS tAH
ROW
T2
tCL
tCH
NOP3
T3
T4
T5
NOP3
READ
NOP
tCMS tCMH
COLUMN m2
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
DQ
tRCD
tRAS
tRC
ENABLE AUTO PRECHARGE
BANK
tAC
CAS Latency
tRP
T6
NOP
t OH
DOUT m
tHZ
T7
ACTIVE
ROW
ROW
BANK
Notes:
1. For this example, BL = 1, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
3. READ command is not allowed else tRAS would be violated.
T8
NOP
Don’t Care
Undefined
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
57
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