MT48LC128M4A2P-7ELITC View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC128M4A2P-7ELITC' PDF : 68 Pages View PDF
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 42: Alternating Bank Read Accesses
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
DQM/
DQML, DQMU
tAS tAH
tCMS tCMH
A0–A9,
ROW
A11, A12
COLUMN m 2
ACTIVE
ROW
NOP
READ
NOP
COLUMN b 2
ACTIVE
ROW
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK 0
ENABLE AUTO PRECHARGE
BANK 0
ROW
BANK 3
ENABLE AUTO PRECHARGE
BANK 3
ROW
BANK 0
tAC
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
DQ
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
t LZ
CAS Latency - BANK 0
DOUT m
DOUT m + 1
DOUT m + 2
DOUT m + 3
tRP - BANK 0
DOUT b
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
Don’t Care
Undefined
Notes: 1. For this example, BL = 4, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
58
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